1. Field of the Invention
The present invention relates to a semiconductor structure and a method of making the semiconductor structure, and more particularly, to a semiconductor structure which can prevent charge loss and block UV light and a method of making the same semiconductor structure.
2. Description of the Prior Art
Non-volatile memories are widely used in modern portable electric devices and a non-volatile memory has an important characteristic of storing data in the memory even though the power is turned off.
FIG. 1 shows a sectional view of a non-volatile memory according to the prior art. As shown in FIG. 1, a transistor 12a and a transistor 12b are positioned, respectively, in the periphery circuits region and the memory array region in the substrate 10. The transistor 12a includes a gate 14a, a gate dielectric layer 16a, and a source/drain doping region 18a positioned in two opposite sides of the gate 14a. The transistor 12b includes a gate 14b, a gate dielectric layer 16b, and a source/drain doping region 18b positioned in two opposite sides of the gate 14b. The transistors 12a, 12b are respectively isolated from each other by an insulator 20. Interlayer dielectric layers 24, 30, 32 are formed on the gates 14a, 14b. A contact plug 22, wires 26 and a via plug 28 are positioned in the interlayer dielectric layers 24, 30, 32 to connect elements and wires electrically.
The interlayer dielectric layer 24 can be a borophosposilicate glass, an undoped silicate glass or other insulating materials. The interlayer dielectric layer 30 is composed of super silicon rich oxide (SSRO) or silicon rich oxide (SRO). The interlayer dielectric layer 32 can be tetraethylorthosilicate (TEOS) based silicon oxide layer or other insulating materials. Because the gate threshold voltage may be shifted by the UV light, the SSRO or SRO of the interlayer dielectric layer 30 is usually utilized as a UV blocking layer in the conventional technology.
The SSRO and the SRO include a high proportion of silicon, and therefore, the etching rate is low. This low etching rate may lead to over etching or insufficient etching of the contact hole if the etching time is not well controlled. Furthermore, the SSRO and SRO may not be removed completely by the etching process due to the low etching rate. The remaining SSRO or SRO in a dead space (a region that is difficult to etch) may lead to a punch though effect. In addition, the conventional non-volatile memory has electricity leakage problem. The electricity leaks usually happen at the top surface of the gates 14a, 14b or between the gates 14a, 14b and the substrate 10.
Therefore, a new structure to solve the electricity leakage and problems caused by the remaining SSRO and SRO is required.